This document specifies secure multiparty computation mechanisms based on garbled circuit. It describes garbled circuit generation, requirements of input label and garbled circuit evaluation. The mechanisms described in this document include free XOR and half gates.
PROJECT
ISO/IEC DIS 4922-3
40.20
DIS ballot initiated: 12 weeks
Mar 16, 2026
To view the full content, you need to register or to log in to your account by clicking on the "Log in" button