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SRPS EN 61523-2:2010

Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

Apr 26, 2010
95.99   Withdrawal of Standard   Nov 29, 2019

General information

95.99     Nov 29, 2019

ISS

N040

European Norm

35.240.50  

English  

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Scope

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

Life cycle

NOW

WITHDRAWN
SRPS EN 61523-2:2010
95.99 Withdrawal of Standard
Nov 29, 2019

Related project

Adopted from EN 61523-2:2002