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SRPS EN 61691-3-3:2010

Behavioural languages - Part 3-3: Synthesis in VHDL

Apr 26, 2010
95.99   Withdrawal of Standard   Apr 28, 2023

General information

95.99     Apr 28, 2023

ISS

N040

European Norm

35.240.50  

English  

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Scope

This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

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SRPS EN 61691-3-3:2010
95.99 Withdrawal of Standard
Apr 28, 2023

Related project

Adopted from EN 61691-3-3:2001